module mode_switch (
    input  sys_clk,
    input  rst_n,
    input  tbase_pulse_i,
    input  btn_sigsel_i,
    input  btn_unitsel_i,
    output sig_sel_o,
    output unit_sel_o
);

  reg  sig_sel_reg;
  reg  unit_sel_reg;

  wire btn_sigsel_revent;
  wire btn_unitsel_revent;

  btn_trig #(
      .N_DELAY(10)
  ) sigsel_trig_inst (
      .sys_clk(sys_clk),
      .rst_n(rst_n),
      .btn_i(btn_sigsel_i),
      .tbase_pulse_i(tbase_pulse_i),
      .btn_revent_o(btn_sigsel_revent),
      .btn_fevent_o()
  );

  btn_trig unitsel_trig_inst (
      .sys_clk(sys_clk),
      .rst_n(rst_n),
      .btn_i(btn_unitsel_i),
      .tbase_pulse_i(tbase_pulse_i),
      .btn_revent_o(btn_unitsel_revent),
      .btn_fevent_o()
  );

  always @(posedge sys_clk, negedge rst_n) begin
    if (~rst_n) begin
      sig_sel_reg  <= 1'b0;
      unit_sel_reg <= 1'b0;
    end else begin
      if (btn_sigsel_revent) begin
        sig_sel_reg <= ~sig_sel_reg;
      end
      if (btn_unitsel_revent) begin
        unit_sel_reg <= ~unit_sel_reg;
      end
    end
  end

  assign sig_sel_o  = sig_sel_reg;
  assign unit_sel_o = unit_sel_reg;

endmodule
